Silicon From Scratch

    Transistor Basics

    Transistors are the building blocks of every modern computer, and yet each one is nothing more than a switch. In this lesson we will look at how that switch actually works, and how just a handful of them, wired together, build the very logic gates we met earlier.

    Think you got this already? Skip to Check Yourself
    A hand-drawn three-dimensional sketch of a transistor: a gray base with a green fin rising through a red gate slab, and two gray metal contacts standing above it, labeled Transistor Basics.

    The Anatomy of a Transistor

    An exploded three-dimensional sketch of a transistor with its layers pulled apart: a gray silicon substrate at the bottom, a green fin standing on it that carries the source, channel, and drain, a thin yellow gate-oxide layer above it, and a red gate that sits across the channel.

    Gate Oxide

    The third part is the gate oxide, a dielectric sandwiched between the gate and the channel. Its job is to stop the gate injecting current into the silicon it controls, while staying thin enough that the gate's field still reaches through.

    It is usually silicon dioxide, SiO2, which is what silicon becomes when heated in oxygen and so can be grown straight out of the wafer.

    Substrate

    The first part of the transistor, and by far the largest, is the substrate. Sometimes called the bulk, it is a moderately piece of silicon that acts as the foundation the whole device is built on. In short, the bulk is the body of the transistor, the block that everything else is formed into and the steady voltage that everything else is measured against.

    Channel

    The second part is the channel, drawn in green and standing on top of the substrate. Its purpose is to provide the road that charge travels along as it crosses from one end of the transistor to the other. At either end of that road we place a region of silicon doped far more heavily than the bulk underneath, and we give those two regions the names source and drain. The channel, then, is simply the stretch of silicon lying between them, and everything the transistor does comes down to whether that stretch is willing to carry current or not.

    Here is a point that surprises most people when they first meet it. The source and the drain are manufactured identically, so if we were handed a transistor on its own, we would have no way of saying which region is which. Their identities are not built into the silicon at all, but they are decided by the voltages we choose to apply once the device is in a circuit. The rule to remember is that charge carriers enter at the source and leave at the drain. In an n-type device the carriers are electrons, which drift from low voltage toward high, so the terminal we hold at the lower voltage becomes the source and the higher one becomes the drain. In a p-type device the carriers are holes, which travel the other way, so that ordering is reversed.

    Gate

    The fourth part is the gate, the piece of the transistor that controls the flow of carriers through the channel. Depending on the voltage applied to the gate, the channel beneath it either fills with carriers and conducts or empties out and blocks. The gate never touches the silicon and never delivers those carriers itself, since the oxide stands in the way. It works entirely at a distance, through the electric field its voltage projects downward.

    The gate is usually made of polysilicon, which is silicon deposited as a mass of small crystals rather than one continuous lattice, and doped so heavily that it conducts much like a metal. Metal would seem the obvious choice, and the earliest devices did use it, which is where these transistors get their name, the metal-oxide-semiconductor, or MOS for short. Polysilicon, though, has a decisive advantage in manufacturing. It survives the high temperatures of the steps that follow, which means the gate can be laid down first and then used as a mask while the source and drain are doped on either side of it. The gate therefore aligns itself perfectly with the channel it controls, and no amount of care aligning a separate mask could match that.

    Applying Voltages

    A hand-drawn cross section of an nMOS transistor: a large p-type substrate with two green n-plus wells sunk into its top surface, wired out to terminals labeled Source and Drain, and between them a thin yellow gate-oxide line under a red gate slab wired out to a terminal labeled Gate.

    With all four parts in hand, we can turn to what the transistor actually does once we begin applying voltages to its terminals. This is where a transistor stops being a stack of materials and starts being a switch, because, depending on what we apply to its terminals, the very same piece of silicon behaves in completely different ways. It helps here to look at the transistor a second way, through a cross section of the same device, which shows all four components again from the side. For this conversation, we will consider a transistor whose diffusions are n-type, marked n+ to show how heavily they are doped, sitting in a p-type substrate. A transistor built this way around is called an nMOS.

    The nMOS cross section with a negative gate-to-source voltage. Negative charge lines the underside of the gate and a row of red plus signs gathers in the substrate just below the oxide.

    Taking the substrate beneath the oxide to be p-type, so the carriers already sitting in it are holes, we start by applying a negative voltage to the gate. Doing so drives the negative charge in the gate down onto its lower face, so it piles up along the interface between the gate and the oxide. With all of that negative charge sitting there, the positive charges, the holes in the channel just beneath the oxide, are pulled up toward it and gather in a thin layer against the underside of the oxide. The silicon at the surface is now even richer in holes than the bulk below it, and because we have gathered extra carriers at the surface rather than removed any, this mode is called accumulation.

    If we instead apply a positive voltage to the gate and slowly increase it, we see the opposite arrangement. Positive charge now collects at the gate side of the interface, and in a similar light as before, it acts on the carriers below. This time it repels the holes in the channel, pushing them down and away from the surface and leaving behind a region emptied of them. What remains there is not nothing. It is the ionized impurities, the dopant atoms themselves, which are locked into the silicon lattice and cannot move. This mode is called depletion, and the name is exactly what you would guess, since we have depleted the surface of holes and left only fixed charge behind.

    If we keep cranking the gate voltage up, the surface eventually runs out of holes to push away, and the field begins pulling electrons toward the interface instead. Past a certain gate voltage, which we call the threshold voltage, written Vth, enough of them have gathered that the surface is no longer behaving as p-type silicon at all. It has flipped into a thin sheet of what is effectively n-type material, stretching from the source to the drain. This mode is called inversion, because the surface has inverted from one type to the other, and it is the mode that finally lays a conducting path between the source and the drain.

    The nMOS cross section with the transistor conducting. The gate voltage is at or above the threshold, a dense layer of electrons fills the channel between the two n-plus wells, an arrow marks the electrons drifting from source to drain, and a purple arrow beneath it marks the current I-DS running the other way, from drain to source.

    Before we can call the transistor on, however, one thing is still missing. Inversion has given us a channel full of free electrons, but a channel full of carriers is not the same as a current. Those electrons will sit where they are unless something pushes them along the channel, and the gate cannot do it, because the field the gate projects points straight down into the silicon rather than from one end of the channel to the other. What we need is a lateral field, one that runs the length of the channel, and we get it by putting a positive voltage on the drain terminal. The drain now pulls on the electrons in the channel, they drift from the source toward the drain, and at last we have movement.

    Here we have to be careful, because current and carriers do not point the same way. Conventional current is defined as the flow of positive charge, so electrons, being negative, travel in the opposite direction to the current they constitute. Our electrons run from source to drain, which means the current runs from drain to source. This is the current the transistor is built to deliver, and we denote it IDS.

    Everything we have just built up describes an nMOS device, and its counterpart, the pMOS, is best understood as the same story with every sign turned around. A pMOS has p-type diffusions in an n-type body, so its carriers are holes rather than electrons, and its threshold voltage is negative. We write the two as Vthn and Vthp to keep them apart. Where an nMOS turns on once VGS rises above Vthn, a pMOS turns on once VGS falls below Vthp, which means pulling the gate down rather than up. The drain sits below the source instead of above it, so VDS is negative, and the holes carrying the charge move from source to drain, which makes IDS negative as well. The practical consequence is the one worth remembering: an nMOS is an active high switch, turning on when its gate is driven high, while a pMOS is an active low switch, turning on when its gate is driven low.

    Putting Transistors in a Circuit

    We now know enough about the device to begin using it, and once we are building circuits out of transistors rather than studying one on its own, the cross section stops being a useful drawing. Nobody sketches doped wells and oxide layers when they are wiring up a circuit. So we meet the transistor a third time, in its schematic form, which throws away everything about how the device is made and keeps only what we need in order to connect it. The terminals are the same ones we have been studying all along. The only difference between the two symbols is the small circle on the gate of the p-type device, which is our shorthand for a transistor that turns on when its gate is pulled low rather than high. Notice too that the source and drain have traded places between the two drawings, which is exactly the point we made earlier: those names follow the voltages, not the silicon.

    The schematic symbol for an n-type transistor: a gate lead entering from the left onto a vertical bar, with the drain leaving from the top right and the source from the bottom right.
    The n-type turns on when its gate is high.
    The schematic symbol for a p-type transistor: the same shape as the n-type symbol but with a small circle where the gate meets the device, and with the source leaving from the top right and the drain from the bottom right.
    The p-type turns on when its gate is low.

    With both symbols in hand we can wire our first circuit, and it turns out one of each is all we need to build the simplest logic gate we met earlier: the inverter. Arranging a combination of nMOS and pMOS in this configuration is referred to as static complementary MOS, or static CMOS. In this configuration, the p-type devices pull the output node up to logic 1, while the nMOS pull the output node down to logic 0. For this reason, the p-type devices of a gate are collectively called its pull-up network, or PUN, and the n-type devices its pull-down network, or PDN. Static CMOS is often the default starting point for VLSI designers when designing a piece of logic because when the device is not switching state, there is no path for current to travel from VDD to ground, limiting the static power consumption of the logic.

    The schematic of a CMOS inverter: a p-type transistor on top with its source tied to V-DD and an n-type transistor below it with its source tied to ground, their gates joined on the left as the input and their drains joined on the right as the output.

    Read the schematic from the outside in. The p-type device sits on top with its source tied to the supply voltage, written VDD, and the n-type device sits underneath it with its source tied to ground. Their gates are joined together on the left and become the single input, and their drains are joined together on the right and become the output. Every transistor in the circuit therefore sees the same input voltage at its gate, which is what makes the pair behave as one device.

    Now recall what each device does with that shared input. Drive the input high and the n-type transistor, which turns on for a high gate voltage, opens a path from the output down to ground, while the p-type transistor, marked with its circle to remind us that it wants a low gate, shuts off. The output is pulled to ground, a logic zero. Drive the input low and the two swap roles exactly. The p-type device opens a path from the supply to the output and the n-type device shuts, so the output is pulled up to VDD, a logic one. A high in gives a low out and a low in gives a high out, which is precisely the behavior of the inverter we met when we were working in logic gates alone.

    Layout on Silicon

    A three-dimensional sketch of a CMOS inverter laid out in silicon: a pMOS transistor in blue and an nMOS transistor in green standing on the substrate and its n-well, with the V-DD and GND metal rails drawn floating above, not yet connected.

    The schematic tells us how the two devices connect, but it says nothing about how they are actually laid out in silicon. The drawing to the left builds that physical picture up in stages. First notice that we are now using two transistors, one nMOS and one pMOS, and we have extended the gate to be over top of both of them. We then connected the input to the gate through a vertical metal pillar called a via. We have connected one end of the pMOS to VDD and one end of the nMOS to ground, just as we did in the schematic. Next, we connect the remaining side of each transistor to each other, which forms the drain-to-drain connection we have on the schematic. Finally, we use another via to pull the output of this circuit from that connection.

    What you are looking at is exactly how an inverter is laid out on real silicon. A finished layout like this one is called a standard cell, and designers keep a library of them, one for every gate they might reach for. Standard cells act like lego bricks. Each one snaps cleanly against its neighbors, sharing the same supply and ground rails, so larger pieces of logic are built simply by tiling the right cells side by side across the wafer.

    Check Yourself

    Which logic expression does this CMOS circuit implement? Choose from one of the four options below.

    A CMOS logic circuit: two p-type transistors in parallel between V-DD and the output y, their gates driven by a and b, and two n-type transistors in series between y and ground, their gates also driven by a and b.
    Continue to Implementing Arbitrary Logic and Stick Diagrams