Learn how processors are actually built.

For students, hobbyists, career-switchers, tinkerers, and the merely curious — young or old. Learn the genius behind the heart of modern computing.

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Your Path

Logic Gates

The building blocks behind even the most complex computing systems. Learn the basics.
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Full Adder

Chain a few gates together and you can add two bits and carry the result — the first real arithmetic in hardware.
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Arithmetic Logic Unit

The engine of the CPU, executing billions of instructions per second. Adders and logic combined into one.
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Single Cycle CPU

The first step in understanding how a processor works. One instruction; one clock cycle.
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Floating Point Adder

Learn the basics of floating point numbers, how they're stored, and how they're added together.
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Pipelined CPU

Learn about pipelining and improve the throughput of your single cycle design.
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Memory Hierarchy

Learn the role memory plays in computing systems, from caches to hard drives, and how the CPU interacts with them.
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Physical Design

Place and route every transistor into a real silicon layout — the floor plan that actually gets fabricated.
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Timing Analysis

Check that every signal settles before the next clock edge — the analysis that sets how fast your chip can safely run.

Hands on

Each lesson comes with a variety of interactive widgets — each of which designed to elevate your learning, get your hands dirty, and put what you've just learned to work.

Cover illustration of a gated D-latch. — Gated D-latch **Stores a single bit** — while `clk` is high the output follows `d`; when it drops low, it holds the last value.

Logic schematic of a gated D-latch. — Gated D-latch **Stores a single bit** — while `clk` is high the output follows `d`; when it drops low, it holds the last value.

Verilog HDL

module gated_d_latch (
    input  wire d,
    input  wire clk,
    output reg  q
);
    // transparent while clk is high; holds when low
    always @(*)
        if (clk)
            q = d;
endmodule

module gated_d_latch (
    input  wire d,
    input  wire clk,
    output reg  q
);
    // transparent while clk is high; holds when low
    always @(*)
        if (clk)
            q = d;
endmodule

q = 0

Interactive Datapaths

Check Yourself

For each sequence below, state whether it must stall, can avoid stalls using only forwarding, or can execute without stalling or forwarding.

Three short RISC-V instruction sequences (A, B, and C) that each set up a data hazard between successive instructions in the pipeline.

A 1-bit ALU: inputs a and b feed an AND gate and an OR gate, whose outputs feed a 2-to-1 multiplexer selected by operation, producing the result.

See the code on GitHub Browse the Verilog behind every project

How to get started

Find the project that's right for you, or begin at the start and work your way through them in order. You don't learn to ride a bike by reading about it! Get going!

Tools Setup Help

Learn how processors are actually built.

Logic Gates

Full Adder

Arithmetic Logic Unit

Single Cycle CPU

Floating Point Adder

Pipelined CPU

Memory Hierarchy

Physical Design

Timing Analysis