Silicon From Scratch
    The top face of an AMD Ryzen 5 9600X processor — the metal heat spreader stamped with the AMD Ryzen logo over a teal substrate.

    Meet the processor

    Where our journey begins

    Every project here is a step toward the silicon you use each day — whether that's in your phone, your computer, or the car you drive. Throughout this journey, we will make references to the AMD Ryzen™ 5 9600X, a powerful processor used in desktop computers.

    Under the covers

    As we take apart the processor, we first see two metallic rectangles — these are called dies. A desktop CPU can have anywhere from one die to well over a dozen, depending on the design. In the Ryzen 5 9600X there are two: an I/O Die (IOD) on top, and a Core Complex Die (CCD), or sometimes called the Compute die, on the bottom. The CCD is like the engine of the processor, executing instructions as fast as possible, while the IOD acts as a communication hub, moving data between the processor cores, memory, graphics card, and the rest of the system.

    Those with a keen eye may notice the large vacant space beside the CCD. This area is intentionally left open as part of a modular design, so the same package can support a second CCD in higher-core-count Ryzen processors, improving manufacturing efficiency and reducing complexity.

    Where the beauty lies

    The real beauty of the silicon actually lives on the underside of the dies. With a special camera, we can see many of the small details on the die — the rows of cores, the dense banks of cache, and the fine wiring that ties them together. What looks like a plain metal rectangle from the outside is, up close, an entire city of circuitry, with every block carefully placed and routed to do a specific job.

    First stop: the L3 Cache

    The image you're looking at now is the CCD. The first major structure that stands out is the L3 cache, a shared pool of 32MB of ultra-fast memory sitting at the center of the CCD. Rather than storing long-term data, the cache acts as the processor's working memory, keeping frequently used instructions and information close at hand so the cores don't have to wait for data to arrive from elsewhere in the system.

    On the die photograph, the L3 cache appears as large, orderly blocks of repeating patterns — dense arrays of tiny memory cells packed together with incredible precision. While the cores do the thinking, the cache keeps the information flowing, quietly feeding data to the processor fast enough to keep billions of operations moving every second.

    Next stop: the cores

    Surrounding the cache are the Zen 5 cores themselves — the parts of the processor responsible for executing instructions and doing the actual work of computation. Whether rendering graphics, compiling code, simulating physics, or running a game, nearly every task performed by the processor ultimately passes through these cores.

    On the die photograph, the cores appear as large, complex blocks filled with smaller structures dedicated to specific jobs: fetching instructions, making decisions about what comes next, performing calculations, and moving data where it needs to go. Together, billions of transistors work in concert, turning streams of electrical signals into the software and experiences we interact with every day.

    AMD's special sauce

    Situated along the edge of the CCD is the IFOP PHY, short for Infinity Fabric On-Package Physical Layer. This high-speed interface links the compute die to the rest of the processor, carrying requests for memory, data destined for the graphics card, and information traveling to and from the I/O die.

    On the die photograph, the IFOP PHY appears as a collection of tightly packed circuitry dedicated not to computation, but communication. While the cores perform calculations and the cache keeps data nearby, the IFOP PHY serves as the CCD's gateway, ensuring information can move quickly and reliably between the processor's many pieces.

    Built to be tested

    Tucked away among the larger functional blocks of the CCD is the Test/Debug circuitry, a collection of specialized hardware used during the processor's development and manufacturing rather than during everyday operation. Before a processor ever runs an operating system or launches an application, engineers rely on these interfaces to verify that billions of transistors are functioning exactly as intended.

    The Test/Debug logic provides a window into the processor's inner workings, allowing engineers to inspect signals, validate designs, and diagnose problems that would otherwise be impossible to observe once the chip is sealed beneath its heat spreader. For example, if a newly manufactured processor fails to boot or produces an unexpected result during testing, engineers can use this circuitry to observe how instructions move through the cores, verify that data is reaching the cache, or confirm that communication between the CCD and I/O die is operating correctly.

    A balancing act

    Sandwiched in the middle is the SMU, or System Management Unit, the part of the processor responsible for power management and overall coordination of how the chip behaves. The SMU is constantly monitoring temperature, power draw, and workload, making real-time decisions about how fast the processor should run and which parts should be active at any given moment. This continuous balancing act helps the processor stay efficient while still delivering performance when it is needed.

    The I/O interconnect is the internal communication network that ties the major functional blocks of the processor together. It moves data between the cores, cache, memory controllers, and other on-die components, allowing them to operate as a single coordinated system. This is different from the IFOP PHY, which specifically handles high-speed communication between the CCD and the separate I/O die outside of it, while the I/O interconnect focuses on traffic within the die itself.

    Going Deeper

    Inside a single core

    We will now begin to explore a single core in detail, zooming into the smallest and most complex part of the CCD. Each core is incredibly rich with dense circuitry, made up of many separate functional blocks that all work together in unison to execute instructions at high speed. What looks like a single unit on a block diagram is, in reality, a tightly packed system of specialized hardware, each part designed for a specific stage of computation.

    A cache of one's own

    The L2 cache is a core's private mid-level memory. Each core gets its own 1 MB that it can access without having to compete with any other core. Because L2 belongs to a single core, it's built directly onto that core rather than in a shared region of the die — keeping it close minimizes the distance signals travel, which is what keeps it fast.

    A cache holds copies of data pulled from main memory, and every stored line carries a tag, a small label recording which memory address it came from. The cache then uses the tag to determine if it actually holds what the core is asking for. In our example, the L2 has a dedicated block set aside just for tags, whereas the L3 most likely distributed its tags across its individual slices, each slice tracking the lines it holds.

    You'll also notice the 1 MB isn't one solid block but two 512 KB banks. Splitting the array shortens the wiring inside each half, so accesses are quicker and draw less power than one large block would.

    Small but speedy

    The L1 cache is the smallest and fastest memory on the core, and the first place the core looks for any instruction or piece of data. Unlike the L2 and L3, it isn't a single pool — it's split into an instruction cache (L1i) holding the code the core is about to run, and a data cache (L1d) holding the values that code operates on. That split exists because the core does both at once: while the front of the core pulls in the next instructions, other parts are busy reading and writing data. Giving each stream its own cache lets the core fetch and move data in parallel instead of competing for the same access. Learn more about pipelining

    The L1i holds 32 KB of ultra-fast memory, while the L1d holds 48 KB — both tiny compared to the L2, which is more than ten times larger. But what L1 gives up in capacity it makes up in speed, running roughly three times faster than the L2 below it. That's the bargain of the whole hierarchy: the closer a cache sits to the core, the smaller and faster it gets.

    Cache hierarchy of a Ryzen 5 9600X (Zen 5). Speeds are approximate, relative to L1.
    Cache Level Size Scope Relative Speed
    L1i 32 KB Private per core Fastest (baseline)
    L1d 48 KB Private per core Fastest (baseline)
    L2 1 MB Private per core ~3× slower than L1
    L3 32 MB Shared across the CCD ~10× slower than L1
    DRAM Many GB System-wide ~50×+ slower than L1

    Coming soon…